Generate floorplan guide documents and SVG diagrams from Verilog/VHDL RTL source code.
npx skills add https://github.com/Paradicat/demo --skill floorplan-guide
Please help me install this Agent Skill. Skill: floorplan-guide Source: https://github.com/Paradicat/demo/tree/main/agent_pack/skills/floorplan-guide Command: npx skills add https://github.com/Paradicat/demo --skill floorplan-guide
This Skill automates the creation of detailed floorplan guides and visual layout diagrams, crucial for physical design teams, by analyzing RTL source code.
Use the floorplan-guide skill to analyze the provided RTL source code and generate a floorplan guide document and SVG diagram.
High-intent search queries and answers about installing and using this skill.
Generating a chip floorplan from RTL source code involves analyzing the design hierarchy and critical paths to estimate module areas. This Skill extracts placement constraints directly from Verilog or VHDL to produce Markdown guides and SVG diagrams for macro placement planning.
RTL analysis for physical design extracts hierarchy, identifies critical timing paths, and estimates module areas directly from hardware description languages. You need it before chip layout planning to define placement constraints and visualize macro arrangements.
Yes, you can visualize placement constraints and module areas by generating SVG diagrams. This Skill creates visual layout representations from the analyzed RTL hierarchy, enabling PD engineers to strategize macro placement and timing-driven layouts.
Creating a PD-ready floorplan guide for macro placement requires extracting design hierarchy and critical timing paths from RTL. This Skill automates the process, outputting actionable Markdown documents with placement constraints and timing-driven strategies.
Yes, this floorplan generation approach works with Verilog and VHDL. It analyzes these RTL formats to extract design hierarchy, estimate module areas, and identify critical timing paths for physical design teams.
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