Compile and run SystemVerilog simulations with Verilator and report PASS/FAIL/ERROR status.
npx skills add https://github.com/RedClaus/cortex --skill gf-sim-redclaus
Please help me install this Agent Skill. Skill: gf-sim Source: https://github.com/RedClaus/cortex/tree/main/core/plugins/gateflow/skills/gf-sim Command: npx skills add https://github.com/RedClaus/cortex --skill gf-sim-redclaus
This Skill automates the compilation and execution of SystemVerilog simulations, providing structured output for easier integration with orchestration tools.
Compile and run the SystemVerilog simulation for the provided DUT and testbench files.
High-intent search queries and answers about installing and using this skill.
You can automate SystemVerilog simulation by compiling Design Under Test and testbench files with Verilator, running the simulation, and parsing the output into standardized PASS, FAIL, or ERROR statuses for CI/CD integration.
Verilator compiles SystemVerilog code by automatically detecting Design Under Test and testbench files, executes the compiled simulation, and captures the output to report simulation status, error counts, and details.
To get structured results from a Verilator simulation, you need a process that parses the simulation output into a standardized format indicating PASS, FAIL, or ERROR status, along with error counts and details.
You do not need to manually specify Design Under Test and testbench files for SystemVerilog simulation if the automation tool automatically identifies these files before compiling them with Verilator and executing the run.
You can integrate SystemVerilog simulation results into orchestration tools by parsing the Verilator simulation output into a structured format that provides standardized PASS, FAIL, or ERROR status reporting for automated workflows.
Aryaman9999Automate end-to-end Verilog/SystemVerilog verification with linting, simulation, and reporting.
mkrlabsGenerate structured QA verdicts and metrics for validation workflows.
codejunkie99Automate SystemVerilog simulation with Verilator and emit GateFlow result blocks.
RedClausGuide SystemVerilog testbench design with layered architectures and verification methodologies.
