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hls-fpga

Automate HLS workflows converting C/C++ kernels into synthesizable FPGA hardware.

Updated Feb 10, 2026
Search Tags:#performance optimization#c++#hls#fpga#rtl design#hardware synthesis
One-click install
npx skills add https://github.com/GhostOf0days/codex-quant-skills --skill hls-fpga
Or copy as Structured Prompt for Agentโ–ผ
Please help me install this Agent Skill.
Skill: hls-fpga
Source: https://github.com/GhostOf0days/codex-quant-skills/tree/main/hls-fpga
Command: npx skills add https://github.com/GhostOf0days/codex-quant-skills --skill hls-fpga

SYSTEM DOCUMENTATION & REQUIREMENTS

๐Ÿ’ก This Skill requires pandas, and includes scripts (resource) and references (resource) components.

What problem does it solve?

This Skill streamlines the process of converting C/C++ algorithm kernels into synthesizable hardware for FPGAs, optimizing performance and resource utilization.

Core Features & Use Cases

  • High-Level Synthesis (HLS): Translate high-level code into hardware descriptions.
  • Pragma Tuning: Systematically optimize hardware by adjusting synthesis pragmas.
  • Equivalence Validation: Ensure the synthesized hardware behaves identically to the original C/C++ model.
  • Use Case: Accelerate a computationally intensive algorithm by synthesizing it into an FPGA kernel, achieving higher throughput than a software-only implementation.

Quick Start

Use the hls-fpga skill to run diagnostics on the input file input.csv and output the results to diagnostics.json.

Frequently Asked Questions about hls-fpga

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I convert C++ algorithm kernels into FPGA hardware?โ–ผ

High-Level Synthesis (HLS) converts C++ algorithm kernels into synthesizable FPGA hardware by translating high-level code into RTL designs. It requires specific pragmas for pipelining, unrolling, and memory partitioning to optimize throughput.

What is the best way to tune HLS pragmas for FPGA throughput optimization?โ–ผ

Tuning HLS pragmas for FPGA throughput optimization involves systematically adjusting synthesis pragmas for pipelining, unrolling, and memory partitioning. This process enables throughput modeling and improves overall hardware performance.

How do I validate C-simulation equivalence against synthesized FPGA hardware?โ–ผ

Validating C-simulation equivalence against synthesized FPGA hardware requires running co-simulation workflows that compare the synthesized hardware behavior against the original C/C++ model. This ensures the generated RTL design matches the software algorithm.

Do I need specific pragmas for pipelining and memory partitioning during hardware synthesis?โ–ผ

Yes, specific pragmas for pipelining, unrolling, and memory partitioning are required during hardware synthesis. These pragmas optimize the generated FPGA hardware and achieve higher throughput than software-only implementations.

Can I use C/C++ for FPGA hardware synthesis instead of writing RTL directly?โ–ผ

Yes, you can use C/C++ for FPGA hardware synthesis instead of writing RTL directly through High-Level Synthesis (HLS). HLS workflows translate high-level algorithm kernels into synthesizable hardware descriptions, improving productivity over manual RTL design.

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