io-ring-orchestrator

Automate IO ring generation by orchestrating the complete workflow from signal classification and device mapping to schematic and layout generation. It supports both T28 and T180 process nodes using a unified T180 workflow pattern, ensuring accurate configuration and reducing manual design effort.

Yes, schematic and layout generation enforces strict signal order and duplicate preservation during pin configuration and JSON construction. This ensures the generated IO ring configuration accurately reflects the intended signal sequence without unexpected reordering or data loss.

The end-to-end workflow coordinates signal classification, device mapping, direction determination, and JSON construction, followed by SKILL code generation and execution. It concludes with automatic DRC and LVS verification to validate the generated IO ring layout and schematic.

Pin configuration and direction determination are handled automatically by coordinating specialized skills during the IO ring generation workflow. You can specify parameters like a 2x2 ring size and clockwise placement to customize the pin assignment for your semiconductor design.

Yes, the workflow handles automatic path determination based on input type to route the IO ring generation process correctly. This ensures the specialized skills for signal classification and device mapping are triggered appropriately for the given semiconductor design inputs.

Manual IO ring schematic generation is complex and error-prone, requiring tedious signal classification and device mapping. Using an automated orchestrator ensures robust DRC and LVS verification while significantly reducing manual effort and potential layout errors across T28 and T180 process nodes.