What problem does it solve?
Designing an HDL-ready Digital Down Converter (DDC) in MATLAB requires correctly coordinating an NCO, mixer, and multi-stage decimation filter chain with fixed-point arithmetic, valid-signal pipelining, and resource-sharing settings — mistakes in any of these produce non-synthesizable or incorrect hardware. This Skill encodes the conventions and workflow so the generated design simulates correctly and converts cleanly to Verilog or VHDL.
Core Features & Use Cases
- End-to-end DDC workflow: Computes NCO phase increments, designs CIC compensation filters with dsp.CICCompensationDecimator, instantiates dsphdl System objects, simulates the streaming chain, and generates HDL via HDL Coder.
- Integer and non-integer decimation: Supports CIC+FIR staging for integer factors and adds dsphdl.FarrowRateConverter for fractional rate changes such as 8.2x or 12.5x.
- Interactive requirements gathering: Prompts for sample rate, carrier frequency, output rate, bandwidth, input data type, decimation staging, CIC sections, and HDL language before generating code.
- Use Case: An engineer needs a receiver front-end that down-converts a 25 MHz carrier sampled at 100 MHz to a 6.25 MHz baseband for an FPGA. The Skill gathers the specs, builds the NCO + CIC(x8) + FIR(x2) chain, simulates it with a modulated test signal, and emits synthesizable Verilog.
Quick Start
Ask the agent to design a Digital Down Converter with dsphdl System objects for your target sample rate, carrier frequency, and decimation factor, then simulate it and generate HDL.
