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pipeline-orchestration

Orchestrate chip design pipeline loops with fix_request management and checkpoint approvals.

180|46|Updated Apr 12, 2026
Search Tags:#pipeline orchestration#iteration management#chip design#checkpoint approval#bug communication
One-click install
npx skills add https://github.com/chuanseng-ng/digital-chip-design-agents --skill pipeline-orchestration-chuanseng-ng
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: pipeline-orchestration
Source: https://github.com/chuanseng-ng/digital-chip-design-agents/tree/main/plugins/meta/skills/pipeline-orchestration
Command: npx skills add https://github.com/chuanseng-ng/digital-chip-design-agents --skill pipeline-orchestration-chuanseng-ng

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires digital-chip-design-agents, and includes scripts (resource) and references (resource) components.

What problem does it solve?

This Skill facilitates cross-domain loop orchestration for the chip design pipeline, providing the fix_request protocol and iteration-cap logic.

Core Features & Use Cases

  • Closed-loop verification–RTL feedback protocol: Coordinates communication of bugs during simulation or formal verification to the RTL orchestrator and ensures the pipeline iterates to resolution.
  • fix_request management: Manages open, claimed, fixed, and abandoned fix_request entries within design_state.json.
  • Iteration cap enforcement: Limits the number of iterations within the pipeline session, triggering an escalation when the cap is reached.
  • Checkpoint approvals: Implements human-in-the-loop gates at configurable stage boundaries for critical decision points.

Quick Start

Use the pipeline-orchestration skill to initiate the closed-loop verification process after detecting a bug in the design.

Frequently Asked Questions about pipeline-orchestration

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I coordinate bug communication between verification and RTL in a chip design pipeline?▼

Bug communication between verification and RTL is coordinated through a closed-loop protocol that sends fix_request entries to the RTL orchestrator, ensuring the pipeline iterates until the design bug reaches resolution.

What is a fix_request protocol for iteration management in chip design?▼

A fix_request protocol manages open, claimed, fixed, and abandoned entries within design_state.json, tracking bug status during the multi-step verification and RTL interaction process.

Can I enforce an iteration cap to prevent infinite loops during RTL fixes?▼

Yes, you can enforce an iteration cap to limit the number of pipeline iterations within a session, triggering an escalation when the maximum number of iterative fixes is reached.

How do I add human-in-the-loop checkpoint approvals at critical pipeline stages?▼

Checkpoint approvals implement human-in-the-loop gates at configurable stage boundaries, pausing the pipeline at critical decision points to await manual review and approval.

Do I need digital-chip-design-agents to use pipeline orchestration?▼

Yes, digital-chip-design-agents is a required dependency, as the pipeline orchestration logic depends on these agents to execute the cross-domain loop operations and verification interactions.

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