Ng Chuan Seng
Community@chuanseng-ng · Singapore
Digital HDL Designer with interest in SW
Agent Skills by Ng Chuan Seng
Showing 16 vetted skills indexed across 1 GitHub repositories.
chuanseng-ngphysical-design
Orchestrate SoC physical design from gate-level netlist to GDS-II.
chuanseng-ngrtl-design
Automate SystemVerilog RTL design with module planning, lint, CDC/RDC, and synthesis checks.
chuanseng-ngembedded-firmware
Develop and validate embedded firmware and drivers for microcontroller platforms.
chuanseng-ngdft
Automate DFT flows including scan insertion, ATPG, MBIST, and JTAG.
chuanseng-ngformal-verification
Prove design properties and check logical equivalence in chip design.
chuanseng-ngsoc-integration
Automate SoC IP integration, bus fabric configuration, and chip-level simulation orchestration.
chuanseng-ngpipeline-orchestration
Orchestrate chip design pipeline loops with fix_request management and checkpoint approvals.
chuanseng-nglogic-synthesis
Synthesize RTL to gate-level netlists with SDC validation and LEC verification.
chuanseng-ngfunctional-verification
Automate UVM-based functional verification workflows for digital chip designs.
chuanseng-ngarchitecture
Optimizes digital chip microarchitecture with gem5, McPAT, and Synopsys Platform Architect PPA estimation and risk assessment.
chuanseng-ngfpga-emulation
Automate ASIC RTL adaptation, synthesis, and bring-up for FPGA prototypes.
chuanseng-nghls
Convert C/C++ algorithms to synthesisable RTL with HLS directives and equivalence verification.
chuanseng-ngmemory-keeper
Merge new learnings from experience records into domain knowledge summaries.
chuanseng-nginfrastructure
Automate EDA tool detection, wrapper deployment, and MCP configuration for chip design environments.
chuanseng-ngcompiler-toolchain
Develop and validate LLVM or GCC compiler toolchains for custom processor ISAs.
chuanseng-ngsta
Automate multi-corner timing analysis and sign-off for chip designs.