formal-verification

Logical equivalence checking verifies RTL against gate-level netlists to ensure synthesised designs match the original logic. It uses formal tools like SymbiYosys and Z3 to mathematically prove equivalence without running simulation testbenches.

CDC verification can be performed using open-source tools like SymbiYosys, Boolector, and Z3, but commercial tools including Cadence JasperGold, Synopsys VCF, and Siemens Questa Formal are also supported dependencies for comprehensive clock domain crossing analysis.

Formal verification mathematically proves design properties hold under all possible conditions, while simulation tests specific test vectors. Formal methods exhaustively verify RTL correctness and logical equivalence without requiring directed or random testbenches.

SymbiYosys and Yosys support exhaustive property proving for chip design by leveraging SMT solvers like Boolector and Z3. This open-source flow enables formal property verification and architectural evaluation without requiring commercial licenses.

Use formal verification when you need to ensure exhaustive correctness of design properties, RTL logic, or clock domain crossings under all conditions. It is essential when simulation cannot cover all possible state spaces or input combinations.