skills.rest
KishoreDamam
KishoreDamamCOMMUNITY
Explore all skills by this author →
WebsiteGitHub

plan-writing

Develop phase-based VLSI project plans with deliverables, dependencies, and validation gates.

1|1|Updated Jan 29, 2026
Search Tags:#project planning#verification#milestones#effort estimation#rtl#timing closure#vlsi
One-click install
npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill plan-writing-kishoredamam
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: plan-writing
Source: https://github.com/KishoreDamam/VLSI-agkit/tree/main/.agent/skills/plan-writing
Command: npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill plan-writing-kishoredamam

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Plan-writing helps you avoid costly RTL churn and schedule surprises by forcing VLSI work to be decomposed into clear phases, deliverables, dependencies, and measurable exit criteria before implementation begins.

Core Features & Use Cases

  • Phase decomposition for VLSI delivery: Breaks projects into Specification, RTL Design, Verification, and Implementation with concrete tasks per phase.
  • Deliverables, dependencies, and effort estimation: Enumerates what must be produced, what external inputs are required, and rough effort ranges to support staffing and scheduling.
  • Validation gates and anti-pattern prevention: Requires objective “done” criteria (e.g., lint/CDC coverage, regression PASS, WNS expectations) and flags common planning mistakes.

Quick Start

Ask the agent to create a repo-checked plan for a multi-week VLSI block including requirements, phase-by-phase tasks, deliverables, dependencies, and objective exit criteria.

Frequently Asked Questions about plan-writing

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I create a project plan for multi-week RTL design and verification work?▼

To create an RTL project plan, structure VLSI work into Specification, RTL Design, Verification, and Implementation phases. This produces a phase-based plan with deliverables, dependencies, effort estimates, and validation gates to prevent schedule surprises.

What is the best way to estimate effort and dependencies for cross-team VLSI coordination?▼

Estimating effort for cross-team VLSI coordination requires enumerating deliverables, external inputs, and rough effort ranges. This supports staffing and scheduling across verification, FPGA bring-up, and software teams by making dependencies explicit.

How do you define objective validation gates and done criteria for timing closure and verification?▼

Objective validation gates for verification and timing closure require measurable exit criteria like lint/CDC coverage, regression PASS, and WNS expectations. This prevents unclear done criteria and flags common planning mistakes before implementation begins.

Can I use this approach to plan FPGA bring-up and software coordination alongside RTL design?▼

Yes, you can plan FPGA bring-up and software coordination alongside RTL design. The plan structures cross-team coordination by making dependencies, milestones, and deliverables explicit across all concurrent VLSI workstreams.

Why does VLSI project planning need explicit milestones and anti-pattern prevention?▼

VLSI project planning needs explicit milestones and anti-pattern prevention to avoid costly RTL churn. Forcing decomposition into clear phases with objective exit criteria prevents missing verification steps and unclear done criteria before implementation starts.

Related Skills

Explore More Product & Management Skills→
jordi-murgojordi-murgo

plan-report

Structure framework plans with project objectives, milestones, and phase-based actions.

Community
Advanced
babywormbabyworm
43

rtl-p4-rapid-impl-policy

Enforce lint, CDC, smoke, and block sanity gates for P4 modules.

Community
Intermediate
zardusai-cyberzardusai-cyber
1

blueprint

Convert a concise objective into a five-phase Markdown construction plan.

Community
Advanced
KishoreDamamKishoreDamam
1

synopsys-flow

Orchestrate Synopsys ASIC front-end steps from RTL synthesis to formal verification.

Community
Advanced