Kishore Damam
Community@kishoredamam
VLSI Engineer | AI Enthusiast
Agent Skills by Kishore Damam
Showing 21 vetted skills indexed across 1 GitHub repositories.
KishoreDamamsynopsys-flow
Orchestrate Synopsys ASIC front-end steps from RTL synthesis to formal verification.
KishoreDamamtcl-scripting
Generate Tcl scripts for automating EDA tool workflows in Vivado, Quartus, and Design Compiler.
KishoreDamamfsm-design
Design and review Verilog/SystemVerilog FSMs with three-process structure and SVA assertions.
KishoreDamamsystemverilog-coding
Guide SystemVerilog RTL coding patterns for logic types, always_ff/always_comb, interfaces, and generate-for pipelines.
KishoreDamamuvm-coding
Implement UVM 1.2 SystemVerilog testbench coding patterns for sequences, drivers, and scoreboards.
KishoreDamamaxi-protocols
Designs and verifies AX4/AX4-Lite/AX4-Stream interfaces with VALID/READY handshake enforcement.
KishoreDamamvivado-flow
Automate Xilinx Vivado FPGA synthesis, implementation, and bitstream generation via Tcl scripts.
KishoreDamamsynthesis-guidelines
Guide RTL authors in preparing synthesizable SystemVerilog for Vivado and Synopsys DC/Genus.
KishoreDamamplan-writing
Develop phase-based VLSI project plans with deliverables, dependencies, and validation gates.
KishoreDamamlow-power-design
Add clock/operand gating and UPF power domains for low-power FPGA or SoC designs.
KishoreDamamcadence-flow
Automate Cadence ASIC front-end synthesis, simulation, and formal verification workflows.
KishoreDamamwaveform-debugging
Guide waveform-driven debugging of RTL simulation failures using VCD/FSDB dumps and signal tracing techniques.
KishoreDamamdft-patterns
Diagnose DFT insertion and ATPG coverage problems in VLSI RTL designs.
KishoreDamambrainstorming
Clarify VLSI project requirements through Socratic questioning.
KishoreDamamquartus-flow
Automate Quartus project setup, compilation, and report extraction using Tcl.
KishoreDamamclock-domain-crossing
Select safe clock-domain-crossing structures for asynchronous signal transfers.
KishoreDamamtiming-constraints
Define and validate SDC/XDC timing constraints for FPGA/ASIC flows.
KishoreDamamclean-rtl
Enforce Verilog/SystemVerilog RTL coding standards for modules, naming, resets, and always_ff/always_comb discipline.
KishoreDamamformal-verification
Write SystemVerilog assertions for formal verification of RTL control paths.
KishoreDamamip-reuse
Package reusable VLSI IP blocks with standardized structure and documentation.
KishoreDamamsta
Diagnose STA setup/hold violations by mapping report_timing fields to the slack equation.