timing-constraints

What problem does it solve?

This Skill helps you author and validate accurate SDC/XDC timing constraints that prevent false STA results and unblock timing closure for RTL, CDC, and vendor-specific FPGA flows.

Core Features & Use Cases

• Clock constraint authoring: define create_clock and create_generated_clock relationships, then verify with report_clocks and CDC/interaction reports.
• I/O timing modeling: set set_input_delay/set_output_delay for system-synchronous interfaces and DDR (including -clock_fall + -add_delay).
• Exception handling for real design intent: apply set_clock_groups, set_false_path, set_multicycle_path (with required hold compensation), and CDC-oriented set_max_delay -datapath_only.
• Xilinx Ultrascale+ XDC additions: add PACKAGE_PIN, IOSTANDARD, and clock routing properties like CLOCK_DEDICATED_ROUTE, plus related XDC patterns for implementation.
• Validation gates and recovery: run targeted checks (e.g., clock interaction, unconstrained IO, exception rationale, CDC tool results) and troubleshoot common STA/XDC failure modes.

Quick Start

Ask the agent to generate a complete SDC/XDC for your design by declaring your primary and generated clocks, adding I/O delays for your board interface, and inserting the correct async/CDC and exception constraints (multicycle/false-path/max-delay), then validate it against the listed reporting gates and fix any unconstrained paths it finds.