formal-verification

SystemVerilog assertions for AXI protocol handshakes encode stable valid/ready behavior, ordering, and reachability using concurrent SVA constructs, property operators, and sequence operators. You structure these proofs with reset disable conditions to reduce vacuous or phantom failures.

Formal verification proves RTL control-path correctness by expressing protocol expectations as SystemVerilog assertions that a formal tool exhaustively analyzes. You need SVA for FSM control paths to discover counterexamples and guarantee properties like exclusivity and state reachability.

Structure assumptions to define environment constraints and cover properties to check reachability for formal verification tools. This setup allows tools like JasperGold or VC Formal to reliably find counterexamples or prove properties without hitting vacuous failures.

Formal verification works with FIFOs and AXI-style interfaces by generating immediate or concurrent SVA constructs. It applies to writing SVA for FSM control paths, arbiters, and bus interfaces, encoding stable-valid/ready behavior and ordering.

SystemVerilog assertions fail vacuously during formal analysis when reset disable conditions are improperly structured or environment assumptions are missing. Structuring proofs with proper reset disabling and adding assumptions for environment constraints reduces these phantom failures.