rtl-p5s-protocol-policy

SVA assertions for AXI protocol verification can be generated using provided assertion templates and naming conventions. These templates cover key AXI rules, burst/size/wrap specifics, and multi-clock domains, ensuring correctness without altering RTL code.

AXI, AHB, and APB bus interfaces should follow specific naming patterns from the slave perspective, with dedicated guidance for master modules and clock/reset naming. Enforcing these port naming conventions ensures consistent signal identification across RTL projects.

Auditing RTL module ports involves reviewing signal names against bus protocol patterns and escalating violations when stop conditions are met. This audit generates a final verification checklist with cycle evidence to produce PASS/FAIL protocol reports.

Protocol violations during RTL verification require escalation when predefined stop conditions are met. The escalation rules guide verification engineers on when to halt reviews and document issues, ensuring critical bus protocol errors receive immediate attention.

Yes, this protocol verification approach explicitly supports AXI4-full specifics, including burst, size, and wrap transactions. It provides targeted SVA assertion templates to validate these complex multi-clock domain behaviors.

The best way to validate AHB and APB signal naming rules is to audit existing RTL module ports against established slave-perspective naming patterns. This checklist-driven review identifies mismatches without requiring modifications to the RTL source code.