rtl-p5s-protocol-policy

What problem does it solve?

Provides a concise, project-aligned policy and checklist to ensure bus protocol correctness and consistent signal naming so verification engineers can write and validate SVA assertions without guessing conventions or missing key rules.

Core Features & Use Cases

• Signal Naming Conventions: AXI, AHB, and APB naming patterns from the slave perspective with guidance for master modules and clock/reset naming.
• Protocol Assertion Patterns: Key AXI rules and SVA assertion templates, plus guidance for AXI4-full specifics (burst/size/wrap) and multi-clock domains.
• Escalation & Checklists: When to escalate, stop conditions, and a final verification checklist to produce PASS/FAIL protocol reports with cycle evidence.
• Use Case: Audit an RTL module's ports, generate required assertion templates, and produce a protocol verification checklist for review.

Quick Start

Ask the skill to audit RTL ports for AXI/AHB/APB naming and produce a protocol verification checklist with SVA assertion templates.