Diagnose STA setup/hold violations by mapping report_timing fields to the slack equation.
npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill sta
Please help me install this Agent Skill. Skill: sta Source: https://github.com/KishoreDamam/VLSI-agkit/tree/main/.agent/skills/sta Command: npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill sta
This Skill helps you interpret static timing analysis results and determine why WNS/WHS fail, so you can close setup/hold violations correctly instead of blindly changing RTL.
Ask an AI coding agent to analyze your failing STA output by walking through report_timing (full_clock_expanded), extracting the key terms (skew, uncertainty, CRPR, derate, and SI deltas), classifying the path group, and recommending the cheapest constraint-then-logic fix with a validation checklist.
High-intent search queries and answers about installing and using this skill.
Static timing analysis setup and hold violations are closed by translating report_timing fields into the slack equation, classifying path groups, and selecting the least disruptive constraint or logic fix before validating with report diffs.
CRPR removes redundant clock path pessimism, OCV applies launch and capture derating, and SI delta-delay accounts for crosstalk impacts on arrival times within the slack equation during static timing analysis.
Interpreting report_timing across MMMC corners requires selecting slow-slow views for setup analysis and fast-fast views for hold analysis, while extracting skew, uncertainty, and derating terms to verify report-to-equation consistency.
Choose OCV for flat path derating, AOCV for depth-based derating, and POCV for statistical variation modeling, selecting based on sign-off realism requirements and static timing analysis flow support.
Timing closure fixes fail validation when ad-hoc changes bypass systematic path classification, meaning the report_timing slack equation terms like uncertainty, derate, or CRPR credit were not checked for consistency before applying the fix.
Latch time borrowing affects setup violation analysis by allowing arrival times to exceed the clock period, requiring specific latch semantics in static timing analysis to correctly classify and close the violation.
konosubakonoakuaExplain Vivado timing and design analysis reports for convergence decisions.
EnigmaWUSeparate fast API queries from slow UI vision tools in agent perception design.
adeleempurpled290Generate XDC/SDC constraints for AMD Vivado FPGA designs.
tangyangchao578-artAnalyze timing violations across corners with MMMC and OCV considerations.
