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KishoreDamam
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axi-protocols

Designs and verifies AX4/AX4-Lite/AX4-Stream interfaces with VALID/READY handshake enforcement.

1|1|Updated Jan 29, 2026
Search Tags:#rtl design#protocol verification#axi#handshake logic#axi-lite#axi-stream#burst and response
One-click install
npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill axi-protocols
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: axi-protocols
Source: https://github.com/KishoreDamam/VLSI-agkit/tree/main/.agent/skills/axi-protocols
Command: npx skills add https://github.com/KishoreDamam/VLSI-agkit --skill axi-protocols

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill solves the confusion and subtle bugs caused by incorrect AXI4/AXI4-Lite/AXI4-Stream handshake, ordering, and response rules that can lead to deadlocks, data corruption, or spec violations.

Core Features & Use Cases

  • AXI4/AXI4-Lite/AXI4-Stream protocol guidance: covers VALID/READY stability, channel dependency ordering, bursts, and stream packetization requirements.
  • Practical RTL implementation patterns: includes interface signal expectations and a sample AXI4-Lite slave write FSM and AXI4-Stream processing pattern.
  • Verification and debugging focus: provides anti-patterns and a checklist for hangs, response correctness (RRESP/BRESP), and AXI-Stream TLAST alignment.

Quick Start

Use the axi-protocols skill to generate a protocol-compliant AXI4-Lite slave that obeys VALID/READY rules and returns correct BRESP/RRESP behavior while handling backpressure safely.

Frequently Asked Questions about axi-protocols

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I prevent deadlocks in AXI4 VALID/READY handshake logic?▼

AXI4-Lite slave write transactions must enforce VALID/READY stability, avoid combinational loops, and return correct BRESP values. This Skill generates protocol-compliant register slave FSMs that handle backpressure safely while diagnosing response ordering issues.

Why does my AXI-Stream datapath drop data at TLAST boundaries?▼

AXI-Stream data drops at TLAST boundaries occur when packetization semantics mismatch transaction boundaries and TKEEP alignment. This Skill validates stream packetization rules and provides RTL patterns to fix TLAST boundary handling and prevent data loss.

How do I verify AXI4 burst and response correctness for DMA masters?▼

AXI4 burst and response correctness for DMA masters is verified by checking RRESP/BRESP values against transaction boundaries and validating channel dependency ordering. This Skill provides anti-patterns and debug checklists to diagnose response errors and ordering deadfalls.

What is the correct way to implement AXI4-Lite CSR slave backpressure?▼

Correct AXI4-Lite CSR slave backpressure implementation requires holding VALID asserted until the transaction is accepted and gating READY without creating combinational loops. This Skill enforces these protocol-stability constraints in the generated write FSM logic.

Can I use this for RTL design and protocol verification of all three AXI variants?▼

Yes, this Skill applies to RTL design and protocol verification across AXI4, AXI4-Lite, and AXI4-Stream interfaces. It enforces handshake behavior, channel dependencies, and burst/response rules suitable for building register slaves, DMA masters, and streaming datapath blocks.

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