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rtl-equivalence-checker

Compare two Verilog RTL designs for functional equivalence and generate counterexamples.

142|14|Updated Feb 14, 2026
Search Tags:#rtl#verilog#design comparison#hardware verification#equivalence checking#counterexample generation
One-click install
npx skills add https://github.com/ArabelaTso/Skills-4-SE --skill rtl-equivalence-checker
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-equivalence-checker
Source: https://github.com/ArabelaTso/Skills-4-SE/tree/main/skills/rtl-equivalence-checker
Command: npx skills add https://github.com/ArabelaTso/Skills-4-SE --skill rtl-equivalence-checker

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires python3, and includes scripts (resource) and references (resource) components.

What problem does it solve?

This Skill automates the verification of functional equivalence between two Register-Transfer Level (RTL) designs, ensuring that modifications or optimizations do not alter the intended behavior.

Core Features & Use Cases

  • Functional Equivalence Checking: Compares two Verilog RTL designs to determine if they behave identically.
  • Difference Analysis: Identifies and categorizes differences as cosmetic (e.g., naming) or semantic (e.g., logic changes).
  • Counterexample Generation: Produces minimal traces to demonstrate functional discrepancies.
  • Use Case: After refactoring a hardware module for better readability, use this Skill to confirm that the refactored version performs exactly the same as the original under all conditions.

Quick Start

Run the equivalence check between 'design_a.v' and 'design_b.v' using the default settings.

Frequently Asked Questions about rtl-equivalence-checker

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I verify functional equivalence between two Verilog RTL designs?▼

Verifying functional equivalence between Verilog RTL designs involves parsing their structure, aligning interfaces and state variables, and analyzing behavioral differences to ensure optimizations do not alter intended behavior.

What is RTL equivalence checking and when do I need it for hardware verification?▼

RTL equivalence checking is a hardware verification process that compares two Verilog designs to determine if they behave identically. You need it after refactoring a module to confirm the refactored version performs exactly as the original.

How do I check Verilog design differences and generate counterexamples for non-equivalent code?▼

Checking Verilog design differences involves categorizing them as cosmetic or semantic, then generating minimal counterexample traces to demonstrate functional discrepancies for non-equivalent designs.

Can I use Python3 to parse and compare Verilog RTL files for code review?▼

Yes, you can use a Python3-based equivalence checker to parse and compare Verilog RTL files. It analyzes behavioral differences and identifies discrepancies to support hardware design verification and code review.

Does RTL equivalence checking distinguish between cosmetic naming changes and semantic logic modifications?▼

Yes, RTL equivalence checking distinguishes between cosmetic differences like naming changes and semantic discrepancies like logic modifications, ensuring that only meaningful behavioral changes are flagged during design comparison.

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