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rtl-p3-uarch-design

Concretize Phase 2 architecture into implementable microarchitecture specifications with TLM-based BFM validation.

43|9|Updated Feb 25, 2026
Search Tags:#compliance#microarchitecture#rtl#hardware-design#bfm#tlm#uarch
One-click install
npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p3-uarch-design
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-p3-uarch-design
Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/rtl-p3-uarch-design
Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p3-uarch-design

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill transforms Phase 2 architecture artifacts into concrete, implementable microarchitecture specifications so teams can move from high-level architecture to RTL-ready module designs while ensuring traceability and validation.

Core Features & Use Cases

  • Orchestrated μArch design: coordinates parallel microarchitecture designers and BFMs rather than doing work directly.
  • Clock domain & protocol allocation: assigns clock domains and communication protocols per sub-block and documents rationale.
  • Resource allocation: decomposes modules into registers, SRAMs, and FSMs with clear ownership and interfaces.
  • TLM-based BFM validation: validates blocks with TLM BFMs and per-block I/O logging before RTL handoff.
  • Compliance & decomposition checks: enforces REQ-U-* acceptance criteria, traces upstream REQs, and reports uncovered critical requirements.
  • Review gating: implements a multi-reviewer acceptance gate and zero-opens invariant to prevent unresolved items from advancing.
  • Use Case: finalize μArch for a cache controller derived from Phase 2 architecture and produce validated per-block specifications and BFM traces for RTL implementation.

Quick Start

Run the rtl-p3-uarch-design skill to produce μArch specifications from docs/phase-2-architecture and validate them with TLM BFMs.

Frequently Asked Questions about rtl-p3-uarch-design

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I concretize high-level architecture into implementable microarchitecture specifications?▼

To concretize microarchitecture specifications, transition Phase 2 architecture artifacts into RTL-ready module designs by assigning clock domains, partitioning protocols, and allocating registers, SRAMs, and FSMs.

How does TLM-based BFM validation work before RTL handoff?▼

TLM-based BFM validation works by validating microarchitecture blocks with Transaction-Level Modeling Bus Functional Models and logging per-block I/O activity to ensure design correctness before RTL implementation.

What is the best way to enforce requirement traceability during microarchitecture design?▼

The best way to enforce requirement traceability is to trace REQ-U-* acceptance criteria back to upstream requirements and report any uncovered critical requirements before advancing the hardware design.

How do I prevent unresolved OPEN items from advancing in hardware design?▼

To prevent unresolved OPEN items from advancing, implement a multi-reviewer acceptance gate that enforces a zero-opens invariant, blocking any microarchitecture specifications with unresolved issues from moving forward.

When do I need clock domain partitioning for RTL module designs?▼

You need clock domain partitioning when transitioning from Phase 2 architecture to Phase 4 RTL, assigning distinct clock domains and communication protocols per sub-block and documenting the rationale.

Can I use this microarchitecture design approach for a cache controller block?▼

Yes, you can finalize microarchitecture for a cache controller by deriving it from Phase 2 architecture to produce validated per-block specifications and BFM traces for subsequent RTL implementation.

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