rtl-p3-uarch-design

What problem does it solve?

This skill transforms Phase 2 architecture artifacts into concrete, implementable microarchitecture specifications so teams can move from high-level architecture to RTL-ready module designs while ensuring traceability and validation.

Core Features & Use Cases

• Orchestrated μArch design: coordinates parallel microarchitecture designers and BFMs rather than doing work directly.
• Clock domain & protocol allocation: assigns clock domains and communication protocols per sub-block and documents rationale.
• Resource allocation: decomposes modules into registers, SRAMs, and FSMs with clear ownership and interfaces.
• TLM-based BFM validation: validates blocks with TLM BFMs and per-block I/O logging before RTL handoff.
• Compliance & decomposition checks: enforces REQ-U-* acceptance criteria, traces upstream REQs, and reports uncovered critical requirements.
• Review gating: implements a multi-reviewer acceptance gate and zero-opens invariant to prevent unresolved items from advancing.
• Use Case: finalize μArch for a cache controller derived from Phase 2 architecture and produce validated per-block specifications and BFM traces for RTL implementation.

Quick Start

Run the rtl-p3-uarch-design skill to produce μArch specifications from docs/phase-2-architecture and validate them with TLM BFMs.