Automate the Phase 4 RTL implementation pipeline for μArch designs.
npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p4-implement
Please help me install this Agent Skill. Skill: rtl-p4-implement Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/rtl-p4-implement Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p4-implement
Phase 4 RTL implementation often requires coordinating multiple tools and teams to produce lint-clean, verified SystemVerilog code aligned with μArch specs. This skill codifies a structured 10-wave pipeline to coordinate writing, linting, fixing, reviewing, bug fixes, unit testing, CDC and protocol checks, refactoring, and final integration, reducing defects and accelerating handoffs.
Initiate the Phase 4 RTL implementation pipeline for the selected μArch modules and monitor lint, unit tests, and reviews.
High-intent search queries and answers about installing and using this skill.
You can automate the end-to-end Phase 4 RTL implementation pipeline to generate lint-clean, unit-tested SystemVerilog modules directly from completed μArch specifications. This structured pipeline coordinates writing, linting, reviewing, bug fixing, and unit testing.
The wave process is a 10-stage structured workflow: Write, Lint, Fix, Review, Bugfix, UnitTest, CDC, Protocol, Refactor, and IntegrationGate. It ensures reliable SystemVerilog module delivery by integrating CDC and protocol verification with structured rework loops.
Yes, completed Phase 3 μArch specifications are required. The pipeline applies specifically when μArch specs are complete and RTL coding is needed, ensuring the generated SystemVerilog modules align with the architectural design.
You run CDC and protocol verification as integrated waves within the Phase 4 RTL pipeline. After unit testing, the pipeline automatically executes CDC and protocol checks, followed by refactoring and a final integration gate to ensure reliability.
The pipeline outputs SystemVerilog modules in rtl/*/*.sv, testbenches in sim/*/tb_*.sv, documentation in docs/phase-4-rtl/, and review records in reviews/phase-4-rtl/. These artifacts provide full traceability for lint-clean, unit-tested code.
You should not use this automated pipeline if your Phase 3 μArch specifications are incomplete or if your project does not require structured CDC and protocol verification. It is designed for multi-module implementations needing strict lint-clean and unit-tested handoffs.
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