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yosys

Write synthesisable Verilog-2005 for iCE40 FPGAs and build bitstreams with the open-source toolchain.

465|41|Updated Aug 4, 2026
Search Tags:#synthesis#rtl#bitstream#fpga#verilog#yosys#ice40
One-click install
npx skills add https://github.com/autonomous-ai/openharness --skill yosys-autonomous-ai
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: yosys
Source: https://github.com/autonomous-ai/openharness/tree/main/store/agents/yosys/skills/yosys
Command: npx skills add https://github.com/autonomous-ai/openharness --skill yosys-autonomous-ai

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve? Writing RTL that actually synthesises is hard: inferred latches, multi-driven nets, blocking assignments in sequential logic, and missing resets silently produce broken hardware. This Skill encodes the exact Verilog-2005 subset, testbench shape, pin constraints, and report-reading knowledge needed to take a design from RTL to a working iCE40 bitstream with Yosys, nextpnr, and Icarus Verilog. ## Core Features & Use Cases - Full open-source flow: One command runs simulation (iverilog/vvp), synthesis (yosys synth_ice40), place-and-route (nextpnr-ice40), schematic generation (netlistsvg), and bitstream packing (icepack), with per-step logs and a JSON report. - Synthesisable subset rules: Enforces default_nettype none, non-blocking assignments in sequential logic, single-driver nets, fully assigned combinational blocks, and sized literals. - Ready-made blocks: Provides tested UART transmitter, PWM, debounce, clock divider, and block RAM inference patterns, plus the iCEBreaker (iCE40UP5K-SG48) pinout. - Use Case: Ask the agent to build a UART echo design for the iCEBreaker; it writes the RTL and testbench, runs the flow, reads the utilisation and Fmax report, fixes timing or latch warnings, and produces a flashable bitstream. ## Quick Start Use the yosys skill to write a blinking LED top module with a testbench, run the full flow, and show me the utilisation and Fmax report.

Frequently Asked Questions about yosys

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I synthesize Verilog for an iCE40 FPGA with open-source tools?▼

Run the flow command with your top module name: it runs iverilog simulation, yosys synth_ice40 for synthesis, nextpnr-ice40 for place-and-route, and icepack to produce the .bin bitstream. Each step logs to out/logs and the report lands in out/<top>.report.json.

What Verilog subset does Yosys synthesise reliably?▼

Use Verilog-2005 with non-blocking assignments in clocked always blocks, blocking assignments in combinational blocks, one driver per signal, sized literals, and fully assigned case/if statements. Avoid initial blocks for logic, delays, while loops, and real types.

Why does Yosys warn about inferred latches in my design?▼

An inferred latch appears when a combinational always @(*) block does not assign an output on every path, such as an if without else or a case without default. Fix it by assigning a default value at the top of the block before any conditional logic.

How do I constrain pins for the iCEBreaker board?▼

Add a set_io line per top-level port in constraints/<top>.pcf, using the iCEBreaker pin numbers such as 35 for the 12 MHz clock and 10/11/37 for the button and LEDs. Every unconstrained top-level port makes nextpnr fail with an unconstrained IO error.

Why does my simulation pass but the hardware behave differently?▼

The usual causes are blocking assignments in sequential logic, multi-driven nets, or sampling asynchronous inputs directly. Use <= in clocked blocks, keep one driver per signal, and pass buttons or UART lines through two synchroniser flip-flops.

How do I fix a failing Fmax timing report in nextpnr?▼

Compare achievedMHz against constraintMHz in the pnr.clocks report; a pass:false means the critical path is too long. Break the path with a pipeline register rather than lowering the clock, and inspect critical_paths in the pnr JSON for the exact hop-by-hop route.

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