XS-MLVPOfficial·13 Agent Skills Included

UCAgent

Automated hardware verification with staged checks and bug analysis

Automates hardware design verification through configurable stages, deterministic checkers, and formal or unit test workflows. Generates SVA assertions, test templates, bug reports, and waveform evidence from a single YAML source of truth. Eliminates manual RTL review, scattered test scripts, and unverifiable results by gating every stage with strict checks.

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npx skills add XS-MLVP/UCAgent --all -g -y

Available:

Gives the agent the repository map, configuration loading order, stage and checker lifecycle rules, and strict constraints for safely editing and running verification workflows.

All Skills in This Repository (13)

Pure Emerald Level Indicators

📦 In Repo

XS-MLVP

ucagent

Automate multi-step task workflows via YAML-configured missions and stages.

sva-audit

Automate SVA environment analysis by filling formal records from verification results.

cex-gen

Generate Python test function scaffolds for RTL bugs from wrapper.sv.

sva-gen

Convert YAML SVA bodies into SystemVerilog assertions for formal checks.

func-spec

Extract DUT functional specifications into hierarchical YAML records via update_spec.py.

bug-report

Scaffold RTL_BUG entries from verification analysis into .formal_records.yaml.

sva-opt

Analyze COI coverage data and generate SVA assertions for uncovered signals.

static-bug-analysis

Analyze RTL designs for static bugs using FG/FC/CK taxonomy.

static-bug-validation

Validate and link static bug analysis placeholders to dynamic bug records.

test-case-implementation-in-batch

Automate batch test-case implementation and structured bug analysis workflows.

create-test-case-templates

Generate standardized test-case templates from Markdown definitions and reference files using Python scripts.

functions-and-checks

Structure DUT functionality into FG/FC/CK hierarchies for test design documentation.

Official

Intermediate

Frequently Asked Questions

FAQPage Schema

How to install UCAgent?▼

Run `npx skills add XS-MLVP/UCAgent --all -g -y` in your terminal to install all skills in this suite globally.

What does UCAgent do for hardware verification?▼

It runs staged verification workflows for chip designs, generating test cases, formal assertions, and bug reports while deterministic checkers block incomplete or fabricated results.

How do I verify my UCAgent config before running?▼

Use the --emulate-config flag with your config file to validate syntax, stages, and checker loading without running the actual task.

Can UCAgent write SystemVerilog assertions automatically?▼

Yes. Its formal skills let the agent draft SVA properties in a YAML record, then automatically render the checker and wrapper SystemVerilog files.

Does UCAgent support custom quality checkers?▼

Yes. You can write custom Checker classes in Python, add their path with --append-py-path, and reference them directly in your YAML stage configuration.