debug-design

What problem does it solve?

This Skill guides engineers through debugging failing HighTide builds by systematically locating the failed stage, reading the relevant artifacts, and ensuring fixes stay within flow parameters rather than modifying the fixed benchmark RTL.

Core Features & Use Cases

• Stage & artifact triage: Detects whether Bazel or Make was used, enumerates available results/logs, and identifies the last successful and first failed stages by inspecting ODB and log files.
• Config-aware diagnosis: Reviews config.mk, constraint.sdc, BUILD.bazel, pdn.tcl, io.tcl, and sram definitions to understand flow parameters, timing constraints, pin placement, and FakeRAM usage.
• Stage-specific remediation: Provides targeted guidance for synthesis, floorplan, placement, CTS, routing, and final timing/DRC reports while showing how to generate layout snapshots, heatmaps, and congestion images for better visualization.
• Testing & verification: Suggests rerunning Make or Bazel flows after adjustments and comparing metrics like WNS, TNS, Fmax, and DRC counts before recommending the /optimize-ppa step.

Quick Start

Use the debug-design skill for asap7/lfsr when Bazel or Make reports a build failure so you can gather artifacts, identify the failed stage, and recommend flow-parameter fixes without touching RTL.