Diagnose failing HighTide designs by correlating build artifacts, logs, and configuration files.
npx skills add https://github.com/VLSIDA/HighTide --skill debug-design
Please help me install this Agent Skill. Skill: debug-design Source: https://github.com/VLSIDA/HighTide/tree/main/.claude/skills/debug-design Command: npx skills add https://github.com/VLSIDA/HighTide --skill debug-design
This Skill guides engineers through debugging failing HighTide builds by systematically locating the failed stage, reading the relevant artifacts, and ensuring fixes stay within flow parameters rather than modifying the fixed benchmark RTL.
/optimize-ppa step.Use the debug-design skill for asap7/lfsr when Bazel or Make reports a build failure so you can gather artifacts, identify the failed stage, and recommend flow-parameter fixes without touching RTL.
High-intent search queries and answers about installing and using this skill.
To debug HighTide build failures without touching RTL, correlate build artifacts, logs, and configuration files to identify synthesis, placement, or routing issues. You can then recommend targeted adjustments to config.mk, constraint.sdc, and pdn.tcl.
Locate the failed stage in a Bazel or Make HighTide flow by inspecting stage-specific directories in bazel-bin or results. You can identify the last successful and first failed stages by reading ODB outputs and log summaries.
When synthesis or routing fails, check configuration files like config.mk, constraint.sdc, BUILD.bazel, pdn.tcl, and io.tcl. Reviewing these files helps understand flow parameters, timing constraints, pin placement, and FakeRAM settings.
Fix timing or DRC violations in an OpenROAD HighTide design by reviewing final timing and DRC reports, then adjusting flow parameters in constraint.sdc or pdn.tcl. You can generate layout snapshots and congestion images to visualize issues before rerunning the flow.
Yes, you can use this diagnostic approach for both Bazel and legacy Make HighTide builds. The process detects which build system was used, enumerates available results and logs, and inspects the corresponding stage-specific directories to read ODB outputs.
VLSIDAOptimize power, performance, and area for HighTide designs by tuning flow parameters.
amoslee2026Automate OpenSTA multi-corner timing analysis and parse results into JSON.
adeleempurpled290Guide selection of Vivado implementation directives and optimization strategies for FPGA designs.
ma08Diagnose failing GitHub Actions checks and extract failure snippets from logs.