optimize-ppa

Optimize power, performance, and area for HighTide designs by tuning flow parameters.

36|13|Updated Jun 8, 2025
One-click install
npx skills add https://github.com/VLSIDA/HighTide --skill optimize-ppa
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: optimize-ppa
Source: https://github.com/VLSIDA/HighTide/tree/main/.claude/skills/optimize-ppa
Command: npx skills add https://github.com/VLSIDA/HighTide --skill optimize-ppa

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This Skill helps engineers wring out higher utilization, faster Fmax, and cleaner DRC-free flows from HighTide benchmark builds without ever editing upstream RTL by focusing on stats-driven flow, timing, IO, and PDN tuning.

Core Features & Use Cases

  • Baseline Measurement: Capture die area, utilization, power, timing, and runtime from bazel-bin logs or legacy logs and reference config.mk, constraint.sdc, BUILD.bazel, io.tcl, and pdn.tcl files before changing anything.
  • Utilization Optimization: Incrementally raise CORE_UTILIZATION and PLACE_DENSITY, mitigate congestion with IO pin scripts, macro halos, pin spacing, and ABC area controls, and watch for runtime blowup or routing failure heatmaps.
  • Timing and Power Tightening: Read timing reports, adjust clock periods, IO delays, and uncertainty settings, rerun flows, monitor CTS/routing stages, and optionally tighten power through IR-drop-aware PDN scripts and ABC_AREA settings.
  • Flow Diagnostics: Generate placement, routing, RUDY, and IR drop images via Docker+OpenROAD, compare metrics across runs in tables, and iterate until additional changes trigger unacceptable congestion or negative margins.

Quick Start

Ask the skill to review the last build metrics for designs/asap7/lfsr, adjust config.mk/constraint.sdc/io.tcl/pdn.tcl to increase utilization and tighten timing, then rerun the flow and compare the new die area, Fmax, and DRC status against the baseline.

Frequently Asked Questions about optimize-ppa

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I optimize PPA for HighTide physical design builds without modifying RTL?

To optimize PPA without modifying RTL, analyze build reports and tune flow parameters like utilization, clock period, and IO placement in config.mk and constraint.sdc files. Iterate by rerunning the flow and monitoring 6_report.json metrics.

How do I increase core utilization in OpenROAD without causing routing congestion?

To increase core utilization without causing routing congestion, incrementally raise CORE_UTILIZATION and PLACE_DENSITY while mitigating congestion using IO pin scripts, macro halos, and pin spacing. Monitor routing heatmaps and runtime to prevent flow failures.

What is the best way to tighten timing constraints for ASAP7 and Sky130HD benchmarks?

The best way to tighten timing constraints for ASAP7 and Sky130HD benchmarks is to read timing reports, adjust clock periods and IO delays in constraint.sdc, rerun the flow, and monitor CTS and routing stages until negative timing margins appear.

Can I use Bazel or Make to run HighTide PPA optimization flows?

Yes, you can use Bazel or Make to run HighTide PPA optimization flows. The process extracts baseline die area, power, and timing metrics from bazel-bin or legacy logs, applies parameter tuning, and reruns the build to compare new metrics.

How do I reduce IR drop and improve power delivery in HighTide PDN scripts?

To reduce IR drop and improve power delivery, tighten power configurations using IR-drop-aware PDN scripts and ABC_AREA settings. Generate IR drop images via Docker and OpenROAD, compare metrics across runs, and iterate until congestion or negative margins occur.

Why does my HighTide flow fail after increasing placement density and utilization?

Your HighTide flow fails after increasing placement density because aggressive utilization triggers routing congestion and runtime blowup. You must monitor DRC reports and RUDY images, adjusting macro halos and pin spacing to mitigate the physical design bottlenecks.