VLSI Design & Automation Group
Official@vlsida · Santa Cruz, CA
UC Santa Cruz VLSI Design and Automation research lab
Agent Skills by VLSI Design & Automation Group
Showing 8 vetted skills indexed across 1 GitHub repositories.
update-design
Audit HighTide2 design submodules, tools, and ORFS dependencies for upstream updates.
debug-design
Diagnose failing HighTide designs by correlating build artifacts, logs, and configuration files.
port-design
Port HighTide designs between technology platforms with Bazel or Make flows.
optimize-ppa
Optimize power, performance, and area for HighTide designs by tuning flow parameters.
openroad-tcl
Provide offline OpenROAD Tcl command documentation with options and examples.
sdc-sta
Provide OpenSTA and SDC command syntax for static timing constraints.
new-design
Create repos, FakeRAMs, and platform configuration files for HighTide2 hardware designs.
find-designs
Search GitHub for synthesizable hardware designs missing from HighTide2.
Frequently Asked Questions About VLSI Design & Automation Group
FAQPage SchemaWhat specific hardware design tasks does this group support?▼
The group supports HighTide2 design lifecycle management, including creating FakeRAMs, auditing submodules, and searching for synthesizable hardware. It provides technical documentation for OpenROAD Tcl commands and SDC syntax to facilitate static timing analysis and physical design optimization.
Which engineering personas benefit from these resources?▼
These resources are designed for hardware engineers, VLSI researchers, and physical design specialists working with the HighTide2 ecosystem. It is particularly useful for those managing complex chip design repositories and requiring precise command-line references for OpenSTA and OpenROAD synthesis environments.
What are the prerequisites for utilizing these design capabilities?▼
Users require a functional environment configured for HighTide2, including Bazel or Make build systems. Access to OpenROAD and OpenSTA binaries is necessary to execute the provided Tcl command documentation and static timing constraint configurations effectively.