Create repos, FakeRAMs, and platform configuration files for HighTide2 hardware designs.
npx skills add https://github.com/VLSIDA/HighTide --skill new-design
Please help me install this Agent Skill. Skill: new-design Source: https://github.com/VLSIDA/HighTide/tree/main/.claude/skills/new-design Command: npx skills add https://github.com/VLSIDA/HighTide --skill new-design
Eliminates the manual chaos of adding new open-source hardware designs to the HighTide2 benchmark suite by providing a complete, repeatable integration playbook that keeps every platform on-spec.
Tell the skill to integrate the new design by naming it and supplying the upstream repo URL so you receive the tailored setup checklist.
High-intent search queries and answers about installing and using this skill.
To add a new open-source hardware design to a benchmark suite, you must clone the upstream repo, identify HDL details, generate FakeRAM artifacts, and author platform configuration files like config.mk and constraint.sdc to meet project conventions.
Onboarding Verilog benchmarks across asap7 and sky130hd platforms requires creating release RTL, defining LEF/LIB definitions, and specifying platform configuration files including constraint.sdc and optional pdn or io scripts to match technology-specific requirements.
FakeRAM integration works by generating specific memory artifacts during the hardware design onboarding process, replacing external memory macros with functional simulators to validate the RTL flow without requiring full physical memory implementations.
Yes, you can use Bazel and Makefile to validate newly integrated hardware benchmarks by registering the new design in the Makefile and running Bazel or Mac build validation to exercise the dev and release RTL flows end-to-end.
The best way to structure platform configuration files for nangate45 benchmarks is to author a config.mk file alongside a constraint.sdc file, adding optional pdn and io scripts to ensure the design follows technology-specific requirements and passes end-to-end testing.
morganpLints and validates Verilog code with Verilator and Verible via temporary files.
gth-aiAutomate branch synchronization, multi-suite testing, and pull request creation.
rigortypeAdd external repositories as reference submodules and update build configuration.
VLSIDAPort HighTide designs between technology platforms with Bazel or Make flows.
