Port HighTide designs between technology platforms with Bazel or Make flows.
npx skills add https://github.com/VLSIDA/HighTide --skill port-design
Please help me install this Agent Skill. Skill: port-design Source: https://github.com/VLSIDA/HighTide/tree/main/.claude/skills/port-design Command: npx skills add https://github.com/VLSIDA/HighTide --skill port-design
This Skill removes the guesswork of porting a HighTide design from one technology platform to another by walking through the necessary configuration, constraint, and memory artifacts so the build flows stay intact.
Tell port-design to port lfsr from asap7 to sky130hd.
High-intent search queries and answers about installing and using this skill.
Design migration across technology platforms requires aligning config.mk, constraint.sdc, BUILD.bazel, and FakeRAM artifacts with the target node's naming and layer conventions. This ensures Bazel or Make build flows remain intact during the porting process.
ASIC design migration to a new platform requires copying and adapting config.mk, constraint.sdc, BUILD.bazel, FakeRAM LEF/LIB generators, pdn.tcl, and io.tcl. These files must be modified to match the destination platform's technical requirements.
Tech node migration requires reviewing source platform configs, BUILD files, and SDCs to derive clock and area scaling ratios. Comparing existing ports helps determine the correct platform constants and scaling ratios for the destination node.
Bazel and Make build flows are supported when porting HighTide designs between platforms. The porting process adapts Bazel references and build configurations to meet the target platform's technical requirements and naming conventions.
Validate a ported design by running Bazel or Make builds and confirming reports, DRCs, and QoR metrics on the new platform. Troubleshoot utilization, halo, and timing settings to resolve any issues encountered during the validation process.
Porting HighTide designs across technology nodes faces limitations including potential mismatches in scaling ratios, platform constants, and layer conventions. The process requires careful adaptation of FakeRAM artifacts and constraints to meet target platform technical requirements.
VLSIDADiagnose failing HighTide designs by correlating build artifacts, logs, and configuration files.
VLSIDAOptimize power, performance, and area for HighTide designs by tuning flow parameters.
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