Generate SystemVerilog exercises and review submitted solutions with progressive hints.
npx skills add https://github.com/RedClaus/cortex --skill gf-learn-redclaus
Please help me install this Agent Skill. Skill: gf-learn Source: https://github.com/RedClaus/cortex/tree/main/core/plugins/gateflow/skills/gf-learn Command: npx skills add https://github.com/RedClaus/cortex --skill gf-learn-redclaus
This Skill provides an interactive platform for learning and practicing SystemVerilog, offering exercises, solution checking, and hints to guide users through complex topics.
Start a SystemVerilog learning session on the 'fsm' topic.
High-intent search queries and answers about installing and using this skill.
You can practice SystemVerilog design by generating topic-based exercises for FSMs, FIFOs, and pipelining, submitting your code for automated review, and receiving constructive feedback.
You can request progressive hints during your SystemVerilog learning session to overcome challenges on topics like clock domain crossing and arbiters without revealing the full solution.
Yes, you can submit your SystemVerilog code for automated solution review using the integrated agent, which analyzes your implementation and provides constructive feedback.
SystemVerilog learning covers hardware design topics including basics, state machines, FIFOs, pipelining, clock domain crossing, arbiters, memory, and protocols.
No specific external tools are required as dependencies; you can start a SystemVerilog learning session directly by specifying a topic like 'fsm' to generate interactive exercises.
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