Automate RTL/IP design flow with specification generation, RTL coding, and verification planning.
npx skills add https://github.com/Paradicat/demo --skill ip-design
Please help me install this Agent Skill. Skill: ip-design Source: https://github.com/Paradicat/demo/tree/main/agent_pack/skills/ip-design Command: npx skills add https://github.com/Paradicat/demo --skill ip-design
This Skill streamlines the entire RTL/IP design process, from initial specification to verification, ensuring consistency and quality.
Use the ip-design skill to create a new IP based on the provided specification document.
High-intent search queries and answers about installing and using this skill.
Spec-driven RTL design generates the initial specification, RTL skeleton, and testbench environment based on your defined deliverables and design targets. This enforces a spec-first methodology to ensure verification plans align with design specs.
Managing IP design project structure is handled by workflow automation that generates file lists, SDC constraints, and Makefiles. This ensures consistency across the hardware development flow from specification to verification.
Spec-driven verification ensures test plans align with design specs and coverage goals. It integrates verification planning directly into the RTL coding phase to maintain quality and consistency throughout the IP design flow.
You can generate SystemVerilog RTL and SDC constraints automatically by providing your design requirements. The automation tool manages project structure and outputs the necessary constraints based on user-defined deliverables.
To start an IP design flow using a spec-first methodology, you need to provide your hardware requirements and specification document. The workflow then generates the initial spec, RTL coding, and verification environment.
ArabelaTsoVerify hardware specifications against Verilog, VHDL, or SystemVerilog RTL implementations.
codejunkie99Guide layered SystemVerilog testbench architecture with verification patterns.
Shinei-Nouzen-ArchGuide Vivado XDC/SDC timing and physical constraint creation for FPGA designs.
codejunkie99Orchestrate SystemVerilog RTL development from planning through verification.
