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jetson-customize-pcie

Configure PCIe controllers on Jetson carrier boards via ODMDATA and device-tree overlays.

1|Updated Jun 12, 2026
Search Tags:#embedded#device-tree#overlay#bsp#pcie#jetson#uphy
One-click install
npx skills add https://github.com/JORDAN0615/bsp_factory --skill jetson-customize-pcie
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: jetson-customize-pcie
Source: https://github.com/JORDAN0615/bsp_factory/tree/main/skills/jetson-customize-pcie
Command: npx skills add https://github.com/JORDAN0615/bsp_factory --skill jetson-customize-pcie

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

Manually configuring PCIe controllers on Jetson Thor or Orin custom carrier boards requires coordinating two separate configuration surfaces (BPMP ODMDATA and kernel device-tree overlays), with mismatches causing silent boot failures, link timeouts, or inconsistent hardware state that is difficult to debug.

Core Features & Use Cases

  • Per-controller PCIe configuration: Enable, disable, or adjust lane width and link speed for individual PCIe controllers on Jetson Thor (Tegra264) and Orin (Tegra234) platforms.
  • Consistency validation: Automatically cross-checks ODMDATA settings against kernel overlay fragments to catch contradictory configurations before they are committed to the BSP source repository.
  • Use case: Resolve issues where a custom carrier's PCIe slot or M.2 receptacle fails to enumerate after flashing, or adjust PCIe settings after running the UPHY lane allocation skill to reallocate lanes across controllers.

Quick Start

Use the jetson-customize-pcie skill to configure PCIe controllers for your active Jetson custom carrier profile after completing the UPHY allocation and carrier derivation prerequisite skills.

Frequently Asked Questions about jetson-customize-pcie

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
Why does my Jetson custom carrier PCIe controller fail to enumerate after flashing?▼

PCIe controller enumeration failures on Jetson custom carriers often occur when BPMP ODMDATA settings and kernel device-tree overlay fragments are misaligned. Cross-checking these two configuration surfaces ensures consistent hardware state and resolves silent boot failures.

How do I configure PCIe lane width and link speed for individual controllers on Jetson Orin?▼

Configuring PCIe lane width and link speed for Jetson Orin involves coordinating per-controller BPMP ODMDATA tokens with kernel device-tree overlay fragments. This process adjusts individual controller settings and commits the validated overlay to the BSP source repository.

Do I need to run UPHY lane allocation before configuring PCIe controllers on Jetson Thor?▼

Yes, UPHY lane allocation and carrier derivation are mandatory prerequisite steps before configuring PCIe controllers on Jetson Thor. Completing these ensures lane reallocation is finished before adjusting per-controller enable state, width, or speed.

Can I validate ODMDATA settings against kernel device-tree overlays before committing to the BSP repository?▼

Yes, consistency validation automatically cross-checks BPMP ODMDATA settings against kernel device-tree overlay fragments. This catches contradictory PCIe configurations and enforces mandatory alignment before producing auditable kernel overlay commits for the BSP source repository.

What causes link timeouts on Jetson Thor custom carrier PCIe slots after UPHY reallocation?▼

Link timeouts on Jetson Thor PCIe slots after UPHY reallocation are typically caused by outdated PCIe controller configurations. Updating per-controller enable state, lane width, and link speed via device-tree overlays resolves the inconsistent hardware state.

Does jetson-customize-pcie support disabling specific PCIe controllers on Tegra234 platforms?▼

Yes, the skill supports enabling, disabling, or adjusting lane width and link speed for individual PCIe controllers on Tegra234 Orin and Tegra264 Thor platforms. It coordinates BPMP ODMDATA and kernel device-tree overlays to apply the per-controller configuration.

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