rtl-ip-instantiate

Generate RTL wrappers for third-party IPs from IP-XACT descriptors.

43|9|Updated Feb 25, 2026
One-click install
npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-ip-instantiate
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: rtl-ip-instantiate
Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/rtl-ip-instantiate
Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-ip-instantiate

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Third-party IP integration is error-prone due to mismatched port names, widths, parameter settings, and missing tie-offs; this skill automates generation of consistent, project-convention RTL wrappers to eliminate transcription bugs and speed integration.

Core Features & Use Cases

  • Automated wrapper generation from IP-XACT descriptors or datasheets producing rtl/ip_wrappers/{ip_name}_wrapper.sv.
  • Enforces project naming and typing conventions (i_/o_/io_ prefixes, logic-only, u_ instance names, clk/rst domain naming) and documents parameter mappings and tie-offs.
  • Integrates lint checks (Verible + slang) and stops/escalates on missing descriptors or port-width mismatches.
  • Use case: wrapping a vendor SRAM or PHY so its ports map to sys_clk/sys_rst_n with explicit tie-offs and parameter comments for downstream verification.

Quick Start

Ask the rtl-ip-instantiate skill to generate an IP wrapper from the provided IP-XACT or datasheet and output rtl/ip_wrappers/{ip_name}_wrapper.sv.

Frequently Asked Questions about rtl-ip-instantiate

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate RTL wrapper modules from IP-XACT descriptors for third-party IPs?

To generate RTL wrapper modules from IP-XACT descriptors, the skill automates instantiation by mapping ports, parameters, and tie-offs. It outputs convention-compliant SystemVerilog files to rtl/ip_wrappers/{ip_name}_wrapper.sv, eliminating manual transcription errors.

What naming conventions should SystemVerilog IP wrappers use for ports and instances?

SystemVerilog IP wrappers should use i_, o_, and io_ prefixes for ports, logic-only signal types, and u_ instance naming. The skill enforces these conventions automatically, applying explicit tie-offs and parameter mapping comments for downstream verification.

Can I automatically lint generated RTL wrappers using Verible and slang?

Yes, you can automatically lint generated RTL wrappers using Verible and slang. The skill integrates these lint checks during wrapper generation to ensure the output SystemVerilog files pass project standards before integration.

What happens if there are missing IP-XACT descriptors or port-width mismatches during wrapper generation?

If there are missing IP-XACT descriptors or port-width mismatches during wrapper generation, the skill stops and escalates the issue. This prevents generating incorrect RTL wrappers and ensures accurate port connections before writing the SystemVerilog file.

How do I automate tie-offs and parameter mapping for vendor SRAM or PHY IPs?

To automate tie-offs and parameter mapping for vendor SRAM or PHY IPs, the skill parses datasheets or IP-XACT descriptors. It then generates SystemVerilog wrappers with explicit tie-offs and parameter comments mapped to your project's clk and rst domains.