rtl-p5b-silicon-validation

What problem does it solve?

Phase 5B silicon validation is critical to ensure RTL designs meet timing, synthesis readiness, and top-level integration requirements before tape-out. This skill automates the silicon-readiness validation process, reducing manual verification effort and tightening signoff gates.

Core Features & Use Cases

• Orchestrates Phase 5B silicon validation for RTL blocks and top integration, coordinating synthesis, constraints, and timing checks.
• Enforces signoff-oriented gates and precise top-integration checks after functional closure, replacing ad-hoc verification steps.
• Use Case: A design team transitions from Phase 5A to 5B can apply this skill to ensure a smooth, auditable silicon-validation flow across blocks and top-level integration.

Quick Start

Invoke the silicon validation orchestrator with an optional --top <name> parameter to validate a specific block.