rtl-silicon-validation-policy

Silicon validation signoff ensures post-synthesis quality by enforcing mandatory checks for constraints, timing, and equivalence. It is required during post-synthesis verification workflows across block and top-level designs to confirm signoff readiness.

Apply a P5B silicon validation policy to enforce mandatory checks for constraints quality, synthesis success, CDC/timing signoff, and top precision regression. This structured workflow provides guardrails for error-prone transitions during verification.

Yes, conditional expert delegation via equivalence validation handles RTL/netlist or ECO delta verification. This delegation explicitly gates on preconditions to ensure error-prone transitions are properly verified before proceeding toward signoff.

Use a standardized state template, such as templates/p5b-state.json, to guide progress and artifacts through the signoff process. This template structures the workflow and ensures consistent tracking from synthesis through final validation.

Yes, the P5B silicon validation policy enforces synthesis success and signoff readiness across both block and top-level designs. It applies comprehensive mandatory checks tailored for both design scopes during post-synthesis verification.