amoslee2026Community·32 Agent Skills Included

Babel

Automated chip design from idea to GDSII layout

Automates the full chip design pipeline from a plain-language idea to PRD, architecture, microarchitecture specs, RTL code, verification, synthesis, and final GDSII layout. Replaces manual EDA scripting and hand-written SystemVerilog with five coordinated pipeline stages and 35 single-purpose commands. Enforces quality gates, requirement traceability, and coverage targets at every stage so designs reach signoff faster with fewer errors.

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npx skills add amoslee2026/Babel --all -g -y

Available:

Tells the agent how to run the five-stage chip design pipeline, which slash commands trigger each stage, and which EDA tool versions and directory conventions to use.

All Skills in This Repository (32)

Pure Emerald Level Indicators

📦 In Repo

amoslee2026

<skill-name-kebab-case>

Provide a frontmatter-driven Skill Unit template with optional resource directories.

bb-invoke-yosys

Automate end-to-end RTL synthesis workflows with Yosys and parallel execution.

bb-collect-coverage

Aggregate Verilator line, branch, and toggle coverage from coverage.dat and simulation logs.

bb-invoke-abc

Automate ABC-driven logic optimization on Yosys BLIF outputs.

bb-trace-signal-path

Trace signal paths through AST JSON from source to sink.

bb-arch

Convert rough architectural ideas into formal chip architecture specification documents.

bb-create-floorplan

Generates Magic floorplan TCL from MAS JSON and netlist data.

bb-gate

Automate pass/fail quality gates for RTL, synthesis, PD, and test artifacts with JSON output.

bb-spec-review

Review PRD, arch_spec, and MAS documents for consistency and feasibility gaps.

bb-mas

Generate chiplet MAS, FSM, datapath, verification, and DFT documentation from architecture specs.

bb-invoke-qrouter

Detail-route placed DEF files using QRouter to produce routed DEF.

bb-invoke-verilator

Compile RTL and testbench, run Verilator simulation, and produce logs, coverage, and VCD.

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Frequently Asked Questions

FAQPage Schema

How to install Babel?▼

Run `npx skills add amoslee2026/Babel --all -g -y` in your terminal to install all skills in this suite globally.

How to design a chip with Babel?▼

Describe your chip idea in plain language, then run /bba-architect to generate the PRD, architecture, and microarchitecture specs. The pipeline then produces RTL, verification, synthesis, and GDSII layout stage by stage.

What EDA tools does Babel use?▼

It wraps open-source tools including Yosys for synthesis, Verilator for simulation, OpenSTA for timing analysis, Magic and KLayout for layout and DRC, Netgen for LVS, and QRouter for routing, all targeting the free ASAP7 7nm PDK.

Does Babel work with Claude Code?▼

Yes. All skills follow the standard SKILL.md format and run directly in Claude Code and other compatible coding agents via simple slash commands.

Can beginners use Babel for chip design?▼

Yes. It ships with a 16-chapter tutorial covering the full AI-native chip design flow, and the agents handle the technical EDA details from your plain-language requirements.