skills.rest
Aryaman9999
Aryaman9999COMMUNITY
Explore all skills by this author →
GitHub

open-verifier-uvm

Generate and run cocotb-driven pyUVM testbenches for Verilog/SystemVerilog DUTs with Icarus Verilog.

6|Updated Apr 11, 2026
Search Tags:#verification#testbench#uvm#verilog#cocotb#pyuvm#icarus-verilog
One-click install
npx skills add https://github.com/Aryaman9999/open-verifier --skill open-verifier-uvm
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: open-verifier-uvm
Source: https://github.com/Aryaman9999/open-verifier/tree/main/.agents/skills/open-verifier-uvm
Command: npx skills add https://github.com/Aryaman9999/open-verifier --skill open-verifier-uvm

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill requires iverilog, python3, pip3, gtkwave, cocotb, pyuvm, and includes scripts (resource) components.

What problem does it solve?

This Skill automates building, running, and analyzing UVM-style verification using cocotb and pyUVM for Verilog/SystemVerilog DUTs, removing manual testbench plumbing and simulation orchestration for Python-based UVM testbenches.

Core Features & Use Cases

  • Automated Environment Validation: Checks for required tools and Python packages and provides installation instructions when missing.
  • pyUVM + cocotb Testbench Generation & Execution: Generates Makefile-driven cocotb test directories, runs Icarus Verilog simulations, and parses pyUVM pass/fail output.
  • Hierarchical DUT Support & Signal Mapping: Scans src/ recursively, maps instance names for cocotb dot-path access, and tailors testbenches for hierarchical designs.
  • Scoreboarding, Edge Cases, and Waveforms: Includes reference-model scoreboarding, edge-case sequences, VCD waveform generation, and an option to launch GTKWave for inspection.
  • Use Case Example: Turn a multi-file Verilog design into a pyUVM testbench that runs constrained-random and directed sequences, reports scoreboard mismatches, and produces VCD traces for debug.

Quick Start

Verify my DUT in src/ using a pyUVM cocotb testbench with Icarus Verilog and produce an uvm_report.md in out/.

Frequently Asked Questions about open-verifier-uvm

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I set up cocotb and pyUVM for Verilog verification?▼

To use pyUVM for Verilog verification, you need Python3, pip3, Icarus Verilog, and the cocotb and pyuvm Python packages installed. This Skill checks your environment for these dependencies and provides installation instructions for any missing components.

How do I run UVM verification on a hierarchical Verilog DUT?▼

To run UVM verification on hierarchical designs, this Skill scans your src/ directory recursively and maps instance names for cocotb dot-path access. It then generates a Makefile-driven cocotb testbench tailored to your hierarchical signal structure.

Can I use cocotb with Icarus Verilog for constrained-random testing?▼

Yes, you can use cocotb with Icarus Verilog for constrained-random testing. This Skill generates pyUVM testbenches that execute constrained-random and directed sequences, automatically parsing pass/fail markers and producing structured verification reports.

Does pyUVM support scoreboard checking and VCD waveform generation?▼

pyUVM supports scoreboard checking and VCD waveform generation through cocotb simulations. This Skill includes reference-model scoreboarding for mismatch detection and outputs VCD waveforms, with an option to launch GTKWave for signal inspection.

Why does my cocotb simulation report X or Z anomalies in the testbench?▼

cocotb simulations report X or Z anomalies when uninitialized or high-impedance states propagate through your Verilog DUT. This Skill actively detects these X/Z anomalies during the Icarus Verilog simulation run and flags them in the structured verification report.

What is the best way to automate UVM testbench generation for Verilog?▼

The best way to automate UVM testbench generation is using a Makefile-driven cocotb build process. This Skill automatically generates the test directory, runs the Icarus Verilog simulation, and outputs an uvm_report.md alongside VCD waveforms for debugging.

Related Skills

Explore More Software Engineering Skills→
Aryaman9999Aryaman9999
6

open-verifier

Automate end-to-end Verilog/SystemVerilog verification with linting, simulation, and reporting.

Community
Advanced
trace1729trace1729
28

hardware-debug-waveform

Map VCD/FST waveform evidence to Chisel/Scala logic and RTL ownership.

Community
Advanced
RakameNouyaRakameNouya

gameobject-destroy

Recursively destroy a GameObject and its children in a Unity scene or Prefab.

Community
Intermediate
KishoreDamamKishoreDamam
1

uvm-coding

Implement UVM 1.2 SystemVerilog testbench coding patterns for sequences, drivers, and scoreboards.

Community
Intermediate