open-verifier-uvm

What problem does it solve?

This Skill automates building, running, and analyzing UVM-style verification using cocotb and pyUVM for Verilog/SystemVerilog DUTs, removing manual testbench plumbing and simulation orchestration for Python-based UVM testbenches.

Core Features & Use Cases

• Automated Environment Validation: Checks for required tools and Python packages and provides installation instructions when missing.
• pyUVM + cocotb Testbench Generation & Execution: Generates Makefile-driven cocotb test directories, runs Icarus Verilog simulations, and parses pyUVM pass/fail output.
• Hierarchical DUT Support & Signal Mapping: Scans src/ recursively, maps instance names for cocotb dot-path access, and tailors testbenches for hierarchical designs.
• Scoreboarding, Edge Cases, and Waveforms: Includes reference-model scoreboarding, edge-case sequences, VCD waveform generation, and an option to launch GTKWave for inspection.
• Use Case Example: Turn a multi-file Verilog design into a pyUVM testbench that runs constrained-random and directed sequences, reports scoreboard mismatches, and produces VCD traces for debug.

Quick Start

Verify my DUT in src/ using a pyUVM cocotb testbench with Icarus Verilog and produce an uvm_report.md in out/.