rtl-p3-uarch-policy

What problem does it solve?

This Skill codifies Phase 3 microarchitecture design policy and checklists to prevent ambiguous designs, missed requirements, and failing validation gates, ensuring μArch outputs are traceable, reviewable, and ready for RTL implementation.

Core Features & Use Cases

• Design Criteria & Checklists: Defines module decomposition, clock domain assignment, protocol selection, pipeline partitioning, and storage allocation rules that teams must follow.
• Traceability & Compliance: Mandates REQ→uArch reverse traceability, iron-requirements schema, and compliance-checker invocation to ensure upstream requirements are fully implemented.
• BFM & Review Gates: Specifies BFM validation gates (compilation, functional match to refC, I/O logging), a 3+ round review protocol with convergence metrics, and escalation rules for unresolved issues.
• Use Case: Run during Phase 3 to validate docs/phase-3-uarch artifacts, generate missing audits (clock-domain maps, protocol assignments, SRAM interface specs), and block Phase 3 exit on unresolved high-risk issues.

Quick Start

Ask the rtl-p3-uarch-policy skill to validate docs/phase-3-uarch for a given module and produce a compliance checklist with missing artifacts and required fixes.