rtl-p3-uarch-policy

To enforce microarchitecture design policy, apply codified rules for module decomposition, clock domain assignment, and pipeline partitioning to ensure RTL outputs are traceable and reviewable. This prevents ambiguous designs and missed requirements before implementation.

Ensuring REQ→uArch reverse traceability requires mandating iron-requirements schemas and invoking compliance-checkers to verify upstream requirements are fully implemented. This confirms that all upstream requirements are fully implemented in the microarchitecture outputs.

BFM validation gates for microarchitecture outputs require successful compilation, functional match to reference C, and comprehensive I/O logging. These gates ensure the bus functional model aligns with the intended microarchitecture before proceeding.

The best way to manage clock domain assignment rules is to generate and validate clock-domain maps alongside protocol assignments and storage decisions. This produces traceable microarchitecture artifacts that satisfy Phase 3 exit criteria.

Running a microarchitecture review protocol requires executing a 3+ round review process with specific convergence metrics and escalation rules for unresolved issues. This dynamic review convergence blocks Phase 3 exit until high-risk issues are resolved.

Microarchitecture designs fail Phase 3 exit criteria when there are unresolved high-risk issues, missing artifacts like clock-domain maps, or incomplete BFM validations. Blocking the exit ensures outputs are ready for RTL implementation.