codejunkie99Community·11 Agent Skills Included

Gateflow-Plugin

Natural-language FPGA design, verification, synthesis, and pin mapping

Generates, lints, simulates, and formally verifies SystemVerilog, Verilog, and VHDL hardware designs from plain-English requests. Eliminates manual testbench writing, cryptic Verilator and Yosys errors, and error-prone FPGA pin constraint files. Routes each hardware task to specialized planners, coders, and debuggers, then loops until the design passes lint, simulation, and synthesis.

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npx skills add codejunkie99/Gateflow-Plugin --all -g -y

Available:

Gives the agent proven SystemVerilog coding patterns, lint fixes, and routing rules so it delegates every hardware task to the right specialist sub-skill and verifies the result before delivering working RTL.

All Skills in This Repository (11)

Pure Emerald Level Indicators

📦 In Repo

codejunkie99

gf-sim

Automate SystemVerilog simulation with Verilator and emit GateFlow result blocks.

gf

Orchestrate SystemVerilog RTL development from planning through verification.

gf-expand

Resolve ambiguous GateFlow intents via clarifying questions and structured handoff payloads.

gf-plan

Generates comprehensive RTL implementation plans for hardware designs before coding.

gf-architect

Map SystemVerilog codebases to generate architecture documentation and module hierarchies.

tb-best-practices

Guide layered SystemVerilog testbench architecture with verification patterns.

gf-lint

Lint SystemVerilog code with Verilator and produce categorized warnings and errors.

gf-learn

Generate SystemVerilog exercises and review submitted solutions automatically.

gf-build

Orchestrate parallel SystemVerilog builds with phase-based decomposition and integration.

gf-router

Route user intents to GateFlow skills or agents with confidence scoring.

gf-summary

Analyze Verilator lint and simulation outputs into structured reports.

Community

Basic

Frequently Asked Questions

FAQPage Schema

How to install Gateflow-Plugin?▼

Run `npx skills add codejunkie99/Gateflow-Plugin --all -g -y` in your terminal to install all skills globally. You will also want Verilator installed for linting and simulation.

Can I create FPGA hardware with plain English?▼

Yes. Describe the module you want, such as a FIFO or SPI controller, and GateFlow plans, generates, lints, simulates, and fixes the RTL until it works.

Does GateFlow support formal verification?▼

Yes. It turns plain-English properties like 'the FIFO never overflows' into SVA assertions and runs SymbiYosys proofs, explaining any counterexamples in simple terms.

Which FPGA boards and tools are supported?▼

It ships curated pinouts and constraint files for boards like iCEBreaker, Tang Nano 9K, and Arty A7, and drives open-source tools including Yosys, nextpnr, Verilator, and GHDL.

Do I need hardware design experience to use GateFlow?▼

No. A built-in learning mode teaches SystemVerilog concepts with exercises, and all tool errors are translated into plain-English explanations with exact fixes.