Shinei-Nouzen-ArchCommunity·8 Agent Skills Included

FPGA-Agent-skills

FPGA synthesis, timing closure, and HLS design exploration

Guides the full AMD Vivado and Vitis HLS flow from C/C++ kernels to bitstream, covering synthesis, constraints, implementation, timing analysis, simulation, and hardware debug. Eliminates guesswork in pragma selection, XDC constraint writing, and timing closure with decision tables based on official UG documentation. Includes a multi-agent design space exploration system that iteratively finds Pareto-optimal HLS configurations for latency and resource use.

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npx skills add Shinei-Nouzen-Arch/FPGA-Agent-skills --all -g -y

Available:

Instructs the main agent to act as an architect and scheduler that parses requirements, coordinates three worker agents, and iteratively explores FPGA HLS design configurations until the Pareto front converges.

All Skills in This Repository (8)

Pure Emerald Level Indicators

📦 In Repo

Shinei-Nouzen-Arch

vitis-hls-synthesis

Converts C/C++ FPGA kernels to RTL using Vitis HLS.

vivado-sim

Plan and execute Vivado simulations for behavioral, post-synthesis, and timing verification.

vivado-tcl

Generate and execute Vivado/Vitis TCL scripts for FPGA design flows.

vivado-impl

Guide FPGA Vivado implementation decisions for timing closure and resource optimization.

vivado-constraints

Guide Vivado XDC/SDC timing and physical constraint creation for FPGA designs.

vivado-debug

Guide selection, configuration, and deployment of Vivado debug cores for hardware debugging.

vivado-analysis

Interpret Vivado timing and QoR reports to guide timing closure decisions.

vivado-synth

Identify optimal Vivado synthesis strategies and attribute configurations for QoR.

Community

Advanced

Frequently Asked Questions

FAQPage Schema

How to install FPGA-Agent-skills?▼

Run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent-skills --all -g -y` in your terminal to install all eight FPGA skills globally.

What FPGA tasks do these skills cover?▼

They cover the complete Vivado/Vitis flow: HLS synthesis, RTL synthesis, XDC constraints, implementation, timing analysis, simulation, TCL automation, and hardware debug with ILA/VIO.

How does the Agentic-DSE system work?▼

A main agent coordinates explorer, exploiter, and innovator workers that mutate and combine HLS designs, validate them through synthesis and co-simulation, and update a Pareto front of optimal configurations.

Which Vivado version do these skills support?▼

All skills are based on AMD Vivado and Vitis 2025.2 documentation, and every TCL command has been verified against that release.

Do I need FPGA experience to use these skills?▼

Basic FPGA knowledge helps, but the skills provide decision tables and step-by-step guidance so your agent can handle constraint writing, timing closure, and debug setup from plain requests.