chuanseng-ngCommunity·16 Agent Skills Included

digital-chip-design-agents

Full digital chip design pipeline from spec to tape-out

Guides the complete ASIC and FPGA chip design flow across 14 domains, from architecture exploration and RTL coding through verification, synthesis, physical design, and tape-out sign-off. Enforces stage-by-stage quality gates, loop-back rules, and closed-loop verification-to-RTL bug fixing without manual tracking. Keeps persistent per-domain memory of failure patterns and tool fixes so every run gets faster and more reliable.

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npx skills add chuanseng-ng/digital-chip-design-agents --all -g -y

Available:

Tells the agent how to behave across all 14 chip design domains: apply quality metrics per stage, report PASS/FAIL/WARN after each step, flag ambiguities before proceeding, and escalate when loop limits are exceeded.

All Skills in This Repository (16)

Pure Emerald Level Indicators

📦 In Repo

chuanseng-ng

physical-design

Orchestrate SoC physical design from gate-level netlist to GDS-II.

rtl-design

Automate SystemVerilog RTL design with module planning, lint, CDC/RDC, and synthesis checks.

embedded-firmware

Develop and validate embedded firmware and drivers for microcontroller platforms.

dft

Automate DFT flows including scan insertion, ATPG, MBIST, and JTAG.

formal-verification

Prove design properties and check logical equivalence in chip design.

soc-integration

Automate SoC IP integration, bus fabric configuration, and chip-level simulation orchestration.

pipeline-orchestration

Orchestrate chip design pipeline loops with fix_request management and checkpoint approvals.

logic-synthesis

Synthesize RTL to gate-level netlists with SDC validation and LEC verification.

functional-verification

Automate UVM-based functional verification workflows for digital chip designs.

architecture

Optimizes digital chip microarchitecture with gem5, McPAT, and Synopsys Platform Architect PPA estimation and risk assessment.

fpga-emulation

Automate ASIC RTL adaptation, synthesis, and bring-up for FPGA prototypes.

hls

Convert C/C++ algorithms to synthesisable RTL with HLS directives and equivalence verification.

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Frequently Asked Questions

FAQPage Schema

How to install digital-chip-design-agents?▼

Run `npx skills add chuanseng-ng/digital-chip-design-agents --all -g -y` in your terminal to install all 16 plugins globally.

What chip design tasks can this automate?▼

It covers the full pipeline: architecture exploration, RTL design, UVM verification, formal proofs, synthesis, DFT, timing analysis, physical design, SoC integration, firmware, and FPGA prototyping.

Which EDA tools does it support?▼

It works with open-source tools like Yosys, OpenROAD, Verilator, and KLayout, plus proprietary tools like Synopsys Design Compiler, Cadence Innovus, and Siemens Questa.

Does it work with Claude Code and Codex?▼

Yes. It ships as a Claude Code marketplace plugin and includes IDE config files for Codex, Copilot, Gemini, and OpenCode.

Do I need chip design experience to use it?▼

Basic hardware knowledge helps, but you describe tasks in plain English and the orchestrators enforce the correct stage sequence, quality gates, and sign-off criteria automatically.